1. Field of the Invention
The present invention relates to automated integrated circuit design and, more particularly, to the design of analog or mixed signal, analog and RF circuit design.
2. Description of Related Art
In circuit synthesis processes in use today, a combination of independent device variables representing device parameters of the circuits are fed into a specialized computer program called a circuit simulator that computes performance features, i.e., performance goals, of the circuit. The circuit simulation process is based on highly complex models of devices and the interconnections between them. The simulation time necessary to characterize all performance goals can be long. Naturally, these times tend to further increase with the increase of the circuit complexity. Furthermore, the nature of the synthesis process is such that a large number of design alternatives, also called design points, are visited in order to find one design point with a desirable combination of performance goals. This process is so time consuming and resource intensive that it is desirable to utilize a parallel computer architecture in order to speed it up and complete it in a reasonable time period. Even so, the circuit synthesis process is still very time intensive and in some cases lasts for several hours to a day.
Finding the optimal design point is a task that follows circuit synthesis. During this process, the circuit designer examines design points generated by circuit synthesis to select a single best design point for circuit implementation on a chip. Although it is possible to increase the efficiency of this process by using advanced visualization and data mining techniques, it is still not possible for the designer to examine regions/gaps in the design space not yet explored by the circuit synthesis algorithm. These regions/gaps result because the circuit synthesis algorithm tries to reduce the number of examined design points in order to arrive at a good design point faster. Therefore, the circuit synthesis algorithm tries to narrow the exploration region and reduce the number of generated design points.
Successfully managing the ever increasing complexity of modem IC design has required continuous improvements to the design process. Central to these improvements is the notion of starting at a high level of abstraction and systematically adding detail as the design progresses through the schematic, layout, chip-assembly and fabrication steps.
Beginning the design process at a high level of abstraction allows the designer to concentrate on the most important tradeoffs and not to become quagmired in the details. However, there are drawbacks. Incomplete information can often lead to poor assumptions and an under-performing final design that must iterate multiple times through the design process to finally reach closure on its performance goals. This is especially true in the case of a mixed signal, analog and RF design where signals are continuous-valued and noise is a critical consideration. This is an undesirable situation for the following simple reason: as design time increases, the time to market increases, and the final profit realized from the IC product decreases.
There are several steps in the design process that can be improved by utilizing a circuit model of a circuit versus a circuit simulator. These include (1) faster design/synthesis with increased quality by iterating through the circuit sizing/synthesis part of the design process and exploring more design alternatives in the process; (2) the ability to communicate how parasitics affect circuit performance goals during the layout process to avoid redesign using a model of device variables to performance goals to compensate for parasitics; (3) assessment of the impact of manufacturing or environmental variations on performance goals; and (4) in a hierarchical design, pre-built models can be used for sub-circuits instead of simulators for faster calculation of performance goals.
Automatic circuit sizing/synthesis utilizing a circuit model is a fast and convenient way to explore a large number of circuit designs in a relatively small amount of time. In the final stage, when a designer needs to explore the generated design space and pick a single point for implementation, this process can be significantly improved by allowing the designer to concentrate on those regions in the design space they find interesting, and then perform more detailed analysis in those regions. Circuit modeling enables rapid and efficient support for this process by generating more design points and performance goal values than the simulator-driven approach. Increased speed also brings another important benefit, namely, the possibility to explore regions of the design space with a finer level of detail, thereby increasing the probability that a better design will be found. Gain is thus twofold: increased speed and increased level of detail.
After the initial, simulator based circuit sizing, a designer tries to produce circuit layouts. By changing the size and/or position of cells and devices and, hence, the placement of wiring in a circuit design, a designer introduces effects on the circuit design not accounted for in the initial circuit sizing. These effects are the result of the size and/or position of cells and devices, wiring placement, as well as the mutual influences of devices called parasitics. Even though these parasitic influences are typically very small, they can noticeably affect the performance goals of the circuit. By utilizing a circuit model in the design process, iterations between sizing and layout utilizing the circuit simulator can be avoided thereby increasing the probability of first pass success.
Circuit models can be utilized to evaluate the influence of parasitics on performance goals. The gain is twofold: first, the process is much faster since using the model is much faster than using a circuit simulator; second, since this process requires a large number of points to be explored (typically an order of magnitude larger than in the sizing/synthesis run), it is appropriate to use a model (instead of the simulator) to generate them (again because of speed). This means that the process of estimating the impact of a large number of different layouts to performance goals can be automated. By increasing the number of explored circuit layouts, the probability that the improved design/layout will be found increases.
Manufacturing variations are variations in device characteristics due to imperfect manufacturing processes. Environmental variations are variations in device characteristics due to environmental variations such as temperature or humidity. Special variables can be introduced in the modeling process to account for these variations. Because of the increased speed and possibility to generate and investigate many more alternatives, the quality of the final design by using circuit models is increased.
Complex circuits are designed and built by using lower-level basic circuits as building blocks. This process is known as hierarchical design, and the underlying modeling process is known as hierarchical modeling. Prebuilt circuit models can be used as building blocks to build models of higher level circuits. The main gain here is that the speed of existing models and their availability eliminates the need to use simulators for at least a part of the already complex circuit whereupon the simulation time is significantly reduced.
What is needed, however, but not disclosed in the prior art, is a method of circuit modeling that avoids the use of a single model building technique to develop the circuit models for each performance goal of a circuit.